Semiconductor memory devices are continually shrinking in size while at the same time increasing in density or volume and operate at lower power. The operation of memory devices are synchronized based on clock signals, which may reach different parts of a memory device at different times. The difference in signal paths results in various problems including having a reduced read time margin, which may lead to data being improperly read from the memory.
One example of a semiconductor memory device, a static random access memory (SRAM), includes a plurality of memory cells arranged in rows and columns. Each memory cell typically includes four or six transistors that form a latch for storing a bit of information. Additionally, each memory cell is connected to one of a plurality of write word lines (WWL) and one of a plurality of read word lines (RWL), both of which extend horizontally across an SRAM array forming a plurality of rows. The memory cells are also coupled to one of a plurality of differential write bit line including WBL and its inverse WBL_. A read bit line (RBL) is also coupled to the memory cells. WBL, WBL_, and RBL all extend vertically across the SRAM array to form a plurality of columns.
Data is written to the memory cells by controlling the voltages on the WWL and providing the data on bit lines WBL and WBL_ to be transferred to the storage node. Data is read from the memory cells by controlling the voltage of the RWL and sensing the resultant voltage that develops on the RBL. The process of writing data to and reading data from the memory cells takes a certain amount of time, which varies based on the distance between the memory cell and the memory controller as well as on the variances across the SRAM due to process, voltage, and temperature (“PVT”).
Consequently, SRAM arrays, and other semiconductor memories such as dynamic random access memories (“DRAMs”), also include tracking circuitry to detect delays in signals transmitted through the array. The delays detected through the use of tracking signals are used to adjust the timing of the memory control signals to help ensure the read time margin is sufficiently long such that data may be properly read from the memory. Although multiple bit cell tracking methods have been implemented to reduce the variations (e.g., in threshold voltage, in memory cell read current, etc.) across the SRAM, problems still arise when the memory is implemented for high voltage and high speed SRAMs. In these situations, the tracking may be too fast for low VDD operation due to different threshold voltages (VT) between the logic and the bit lines. Additionally, in some approaches, if the tracking methodology is implemented for low VDD operation, then the tracking may result in too high a read time margin and therefore will not be optimized for normal VDD operation.